DI-EDRS-81339

Integrated Circuit Cell/Functional Sub-Block Data Notebook

This data is to be prepared in the process of developing an integrated circuit cell/functional sub-block standard library.

Approval DateJuly 1, 1993

AMSC NumberG6929

Preparing Activity—

Project Number—

OPRG/Y27

DTIC Applicable—

GIDEP Applicable—

Limitation—

Applicable Forms—

Approval Limitation—

Form VersionAPR 89

DID Formatdd_form_1664

963C CompliantNo

DISTRIBUTION STATEMENT A: Approved for public release; distribution is unlimited.

Supersedes

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Description & Purpose

This data is to be prepared in the process of developing an integrated circuit cell/functional sub-block standard library.

This data will be used to document these cells/functional sub-blocks in detail sufficient to perform artwork topological design rule checking, circuit analysis, cross referencing to the logic symbol and logic diagram, and as an engineering document to be used in the design of integrated circuits using these cells/functional sub blocks.

Application & Interrelationship

This data item description contains the format and content preparation instructions for the data product generated by the specific and discrete task requirement as delineated by the contract.

Used on programs where either cost/schedule control system criteria, in accordance with DOD Instruction 7000.2, or cost/schedule planning and control system requirements are to be applied.

Use & Relationship

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Preparation Instructions

10.1Reference documents.The applicable issue of the documents cited herein, including their approval dates and dates of any applicable amendments, notices and revisions, shall be as specified in the contract.

10.2Format.The document shall be prepared on 8 1/2 x 11 inch paper using nonfading ink suitable for reproduction. This document shall be bound together between a rigid binder.

10.3Content.The Notebook shall contain the following data for each cell/functional sub-block used on or developed for use in the design of integrated circuits whether prepared by automated layout, digitizing, interactive graphics, or manual layout.

10.3.1Title Page

10.3.2Index

10.3.3Design Criteria/Objectives and Analysis Description

10.3.4Design Rules: (1) Electrical (2) Topological

10.3.5Cell/Functional Sub-Block Data Sheet

10.4Title Page.The Title Page shall contain the following information:

10.4.1Contract Short Title

10.4.2Contract Number

10.4.3Contractor Name and Address

10.4.4Integrated Circuit Technology Name

10.4.5Date Prepared

10.5Index.An index reference by page number shall be prepared to facilitate location of material contained in the document.

10.6Design Criteria/Objectives and Analysis Description.This section shall contain a detailed description of the design criteria/objectives, the analysis performed to meet these objectives, and the results of the analysis. The design criteria/objectives shall describe the goals in areas such as frequency, propagation delay, drive capabilities, noise immunity, supply voltages ranges, input and output levels, unique interface constraints, clock levels and waveforms, cell/functional sub-block fanout or levels of propagation constraints, etc. The analysis performed during design shall be described along with the results of the analysis demonstrating the design goals have been met. Where computer modeling of circuits are used in the analysis, a description of the model and modeling equations along with the process parameters used in the analysis shall be described.

10.7Design Rules.This section shall describe the semiconductor process electrical parameters limits (min, max, typical values) over which the cells/functional sub-blocks are designed to operate. It shall also contain a description of the topological design rules used in the layout of the cells/functional sub-blocks.

10.8Data Sheets.The data sheet shall contain the following information:

10.8.1Cell/functional Sub-Block Number.The cell/functional sub-block's number shall be consistent with the numbering used on other integrated circuit data items (i.e., logic diagram and composite/map).

10.8.2Schematic Circuit Diagram.This shall show the interconnection of transistors, resistors, etc., which make up the cell/functional sub-block. The transistor device sizes, resistor values, etc., shall be labeled. The input/output connections shall be labeled and shall correspond with the labeling on the logic symbol and logic diagrams for cross-referencing one to the other.

10.8.3Cell/Functional Sub-Block Logic Symbol.Using ANSI-Y32.19, Graphic Symbols for Logic Diagrams, shall be the symbol used on the logic diagrams used to specify the logical function of the integrated circuit. The input/output connections shall be labeled and shall correspond to labeling used on the logic diagram. This is to be used for cross referencing and determining the actual as built interconnections of the cells/functional sub-blocks on the chip on a one for one basis. The above applies to digital integrated circuits.

10.8.4Logic Equation or Truth Table.The logic equation or truth table for the cell/functional sub-block shall be shown.

10.8.5Input Output Terminal Capacitances or performance Curve.The input and output capacitances of the cells/functional sub-blocks shall be specified. If appropriate, performance or propagation delay curves shall be shown.

10.8.6Design or Usage Notes.Any restrictions or usage notes or comments shall be specified on the data sheet. Items such as clock phase for phased logic cells, special power connections, etc., shall also be specified.

References

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