DI-EDRS-81340

Integrated Circuit Chip and Cell Logic Simulation and Test Pattern Verification Report

Documents the logical description of each cell and chip used for simulation and test pattern verification of an integrated circuit, including normal and faulted configurations.

Approval DateJuly 1, 1993

AMSC NumberG6930

Preparing Activity—

Project Number—

OPRG/Y27

DTIC Applicable—

GIDEP Applicable—

Limitation—

Applicable Forms—

Approval Limitation—

Form VersionAPR 89

DID Formatdd_form_1664

963C CompliantNo

DISTRIBUTION STATEMENT A: Approved for public release; distribution is unlimited.

Supersedes

—

DI-MCCR-80499DI-MCCR-80500

Description & Purpose

This data is the documentation of the logical description of each cell and chip used for simulation and test pattern verification of an integrated circuit. This description will include both the normal and faulted configurations of each cell and chip.

Application & Interrelationship

This Data Item Description (DID) contains the format and content preparation instructions for the data product generated by the specific and discrete task requirement as delineated in the contract.

This data item interrelates with DI-MCCR-80499 and DI-MCCR-80500.

Use & Relationship

—

Preparation Instructions

10.1Format.The report shall be prepared using on 8 1/2 x 11 inch paper. Throughout this data item the term "cell" shall be defined as "a primitive logic element"; e.g., Inverter, NAND, NOR, flip-flop, etc., and shall not include complex functions such as counters, registers, etc.

10.2Contents.The Integrated Circuit Chip and Cell Logic Simulation and Test Pattern Verification report shall include:

10.2.1A description of the type of faults to be detected.

10.2.2A brief description of the computer program and or manual technique used in the simulation and test pattern verification shall be provided and shall include:

10.2.2.1The name of the computer program and, if available to the Government, where it can be obtained.

10.2.2.2The data and revision of the program used.

10.2.2.3The number of faulted and normal states that can be simulated or verified, e.g. 0, 1, X, etc.

10.2.2.4A description of the conditions required for a fault to be considered detected.

10.2.2.5A complete list of assumptions made (if applicable) in modeling cells and performing chip simulations and test pattern verifications.

10.2.2.6A complete description of the logic implementations of each cell shall be provided. This description shall include:

10.2.2.6.1Logic diagram describing logical implementation.

10.2.2.6.2Logic truth table including the normal and faulted conditions.

10.2.2.6.3A list for each cell of any normal or faulted condition not included in the logical model due to limitations in the computer program manual technique, etc.

10.2.3The listing(s) of the chip simulation and test pattern verification shall be provided. Sufficient data shall be provided with the listing to enable the Government to interpret the form and format of the listing(s). This listing(s) shall include:

10.2.3.1The input stimulus and response of the normal or unfaulted condition of the chip. This stimulus shall be identified to the input used in test pattern verification.

10.2.3.2A list of the undetected faults clearly identified and traceable back to the chip logic diagram.

10.2.3.3The percent test pattern grading level achieved with the input stimulus provided.

References

—

Schema v3.0Community-maintained · Verify against ASSIST

Community-maintained — not an official government database.
Verify against ASSIST·GitHub·About·Disclaimer