DI-QCIC-80924A
Semiconductor Process Specification
The Semiconductor Process Specification describes the electrical parameters and topological design rules required for fabricating semiconductor integrated circuits, used as a procurement specification to assure equivalent circuit performance.
Approval DateNovember 8, 2006
AMSC Number7631
Preparing Activity—
Project Number—
OPRNS/DA023
DTIC Applicable—
GIDEP ApplicableNone
Limitation—
Applicable Forms—
Approval Limitation—
Form Version—
DID Formatdd_form_1664
963C CompliantNo
DISTRIBUTION STATEMENT A: Approved for public release; distribution is unlimited.
Application & Interrelationship
—
Use & Relationship
The Semiconductor Process Specification describes the electrical parameters/characteristics and the topological design rules (artwork layout) required for the fabrication of semiconductor integrated circuits. It includes information on the derivation of these parameters, and the testing requirements to verify accuracy. The data is used as a procurement specification to assure that equivalent circuit performance can be obtained for suppliers.
This Data Item Description (DID) contains the format and content preparation instructions for each tech data product generated by the specific and discrete task requirement as delineated in the contract.
This DID is used on systems/equipment acquisitions where semiconductor integrated circuits are designed and fabricated.
This DID supersede DI-QCIC-80924
Preparation Instructions
1Reference documents.None.
2Format.The data shall be prepared in contractor format on 8 1/2 x 11" (metric size A4) bond paper. Drawings and illustration fold-outs may be used, but must not exceed 8 1/2 x 11" limits when folded. Photo-reduction of oversized pages is preferred, provided such reductions are easily readable and reproducible.
3Content.The report shall contain the following information:
3.1Cover/title page.The following information shall appear on the cover and title page:
3.1.4Contractor name and address
3.1.5Processing facility name and address
4.1Electrical Parameters/characteristics.For each of the design parameters listed in Table 1, the following shall be specified:
4.1.1Parameter value/characteristics in the form of histograms, distributions, minimum/maximum or typical values.
4.1.2The sample size upon which the values were based, where applicable.
4.1.3Information on parametric circuits used to determine and quantify the parameters.
4.1.4The test set-up procedures, and conditions under which the parameters values were determined.
4.2Topological design rules.This section describes the topological (artwork layout) design rules to be followed in the layout of the fabrication process. For each applicable areas listed below, a pictorial representation of the layout rule shall be included reflecting associated minimum, maximum, or typical values sufficient to permit layout or modification of the circuit layout.
4.2.3Transistor device geometric
4.2.4Contact design for level-to-level interconnect
4.2.6Diffusion-diffusion spacing/overlap
4.2.7Bonding pad sizes and spacing to scribe line and circuit areas.
4.2.8Scribe area description.
4.2.10Standard test devices
4.2.11Numerical mask and artwork level identification including:
4.2.11.1level nomenclature
4.2.11.2Fiduciary markings
4.2.11.3Coloring/crosshatching used to distinguish levels
4.2.11.4Polarity of each mask level
Figures
Figure Table 1. Electrical Parameters
Schema v3.0Community-maintained · Verify against ASSIST 