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DI-SESS-82498

Built-In Test (BIT) Data / Test Verticality Report

Documents the technical BIT design implementation, false alarm mitigation strategies, and the fault detection and fault isolation model used for aircraft integration, design, assessment, and procurement.

Approval DateJuly 25, 2025
AMSC NumberN10594
Preparing ActivityAS
Project NumberSESS-2025-025
OPR—
DTIC Applicable—
GIDEP Applicable—
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DID Formatfree_text
963C CompliantYes
DISTRIBUTION STATEMENT A: Approved for public release; distribution is unlimited.
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Description & Purpose

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Use & Relationship

The Built-In Test (BIT) Data / Test Verticality Report documents the technical BIT design implementation in sufficient detail to perform aircraft integration and determine whether all the BIT interface requirements have been met. The intent is to assure proper BIT philosophy, hardware/software planning and design coordination, configuration management, and development of logistics capabilities (e.g., Automated Maintenance Environment (AME)/ Configuration and Fault Reporting System (CFRS), tech pubs, etc.). It also documents false alarm mitigation strategies, to guide the software design. Finally, the report includes the fault detection and fault isolation model for the equipment used in the design, assessment, and procurement specifications.

This DID contain the format, content, and intended use information for the data product resulting from the work task described in the contract Statement of Work (SOW).

Preparation Instructions

1Reference documents
1.1DI-SESS-82078A, Integrated Health Management System (IHMS) Description and Data Architecture (DDA)(available at https://quicksearch.dla.mil.)
1.2DI-SESS-81497B, Reliability and Maintainability Predictions Report(available at https://quicksearch.dla.mil.)
1.3DI-SESS-81603, Maintainability and Built in Test Demonstration Report(available at https://quicksearch.dla.mil.)
1.4DI-SESS-81604B, Maintainability and Built in Test Demonstration Procedure(available at https://quicksearch.dla.mil.)
2FormatThis report is to be provided in an electronic format. The BIT Fault Detection (FD)/Fault Isolation (FI) worksheet is to conform to the provided format, and any modifications to the content or format defined therein require written NAVAIR approval. Additional columns or data may be added to facilitate computations as desired.
3Content
3.1External document referencesThe following ground rules are to be observed for referencing external documents. References for external documents are only permitted for the Built-in Test Design Requirements Data section of this report. The inclusion of external documents via appendices to this report is preferred. If the applicable data of an external reference can be condensed to less than five (5) pages, its text should be contained in this report. Where applicable to items in this report, specific paragraphs, tables, figures, etc., should be referenced instead of global references to external documents. Only direct references are to be used; reference documents should not "chain-reference" other reference documents. A preface summary table of references, listing all external references used, including revision letters and dates, and specific paragraphs, figures, tables, appendices, etc., is also to be provided for this report. Prior to being referenced by this report, each externally referenced document must have been delivered to NAVAIR, preferably in electronic format.
3.2Description
3.2.1Built-in-test (BIT) design requirements dataThis section of the report documents the technical BIT design implementation in sufficient detail to perform aircraft integration and determine whether all the BIT interface requirements have been met. The intent is to assure proper BIT philosophy, hardware/software planning and design coordination, configuration management, and development of logistics capabilities (e.g., AME/CFRS, tech pubs, etc.). At a minimum, this section includes the following information:
3.2.1.1A general description of the avionics hardware, BIT specification requirements, and avionics BIT design philosophyThis description addresses system operation, system-level BIT hardware/software allocations, and BIT hardware test signals. Include descriptions of any BIT-induced system inhibit or interrupt commands along with justification for implementation if required. If applicable, provide a detailed description of all system calibrations and system-level BIT tests. DATA DELIVERY: INITIAL, update at INTERMEDIATE and update at FINAL.
3.2.1.2A description of the system operation and system maintenance support concept at the organizational, intermediate, and depot levels of maintenanceInclude, at a minimum, the role of BIT and support equipment at each level. DATA DELIVERY: INITIAL, update at INTERMEDIATE and update at FINAL.
3.2.1.3A detailed description of the power subsystemIncluding power recycling, overload protection features, and all self-test features, as applicable. DATA DELIVERY: INTERMEDIATE and update at FINAL.
3.2.1.4A family tree drawing for each Weapon Replaceable Assembly (WRA) / Line Replaceable Unit (LRU)Graphically illustrating the hierarchical relationship between its assemblies is to be provided. The drawing(s) clearly shows the composition of the WRA / LRU from highest to lowest level of assembly down to and including the sub-Shop Replaceable Assembly (sub-SRA) / Shop Replaceable Unit (SRU) level, with the name and part number of each assembly identified. DATA DELIVERY: INITIAL, update at INTERMEDIATE, and update at FINAL.
3.2.1.5Data describes the design of each Weapon Replaceable Assembly (WRA) / Line Replaceable Unit (LRU) and Shop Replaceable Assembly (SRA) / Shop Replaceable Unit (SRU)Including a block diagram, a description of assembly operation, and a detailed description of Built-In Test (BIT) features. For SRAs / SRUs with embedded self-test (e.g., Autonomous Self-Test, Built-In Self-Test, etc.), include a description of the BIT coverage achieved as well as the method for executing the self-test under the applicable system BIT modes. DATA DELIVERY: INTERMEDIATE and update at FINAL.
3.2.1.6Provide schematic data that is easily traceable to the information contained in the Built-In Test (BIT) analysis worksheets defined in Part C of this documentThese schematics are to be marked to identify the functions within the Weapon Replaceable Assembly (WRA) / Line Replaceable Unit (LRU) and to identify the BIT tests that test each function. DATA DELIVERY: INTERMEDIATE, and update at FINAL.
3.2.1.7A description of all aircraft BIT and maintenance interfacesIncluding the following: DATA DELIVERY: INITIAL, update at INTERMEDIATE and update at FINAL.
3.2.1.7.1Justification for usage of any physical BIT indications(e.g., LEDs, mechanical BIT indicators).
3.2.1.7.2A block diagram and technical description of the avionics system's BIT hardware/software interface to the aircraft hardware/software
3.2.1.7.3Technical descriptions and illustrations of all BIT displays for tactical mode assessment and degraded performance(if applicable), maintainer BIT data, and fault isolation results.
3.2.1.7.4The organization of all BIT matrix data provided to the Mission Computer over the MIL-STD-1553 multiplex bus(or equivalent). A BIT failure code cross-reference table identifying the BIT modes and tests generates the following:
3.2.1.7.4.11553 System/Sub-system Fail Codes(e.g., Go/No-Go, Over-temperature, Checksum status).
3.2.1.7.4.2Operational Flight Program (OFP) Error Codes(e.g., OFP recognized errors/failures to be included in the fault log).
3.2.1.7.4.3Weapon Replaceable Assembly (WRA)/ Line Replaceable Unit (LRU)Identifies the System WRA (LRU) failure status BIT set (if required by Configuration Identification and Data System (CIDS)).
3.2.1.7.4.4BIT ModesIdentifies the BIT mode of the test that generates the failure code Periodic Buit-In Test (PBIT) or Initiated Built-In Test (IBIT).
3.2.1.7.4.5Section (B) BIT Description Paragraph NumberIndicates the location of the test summary, addressing the fail code and the corresponding BIT test.
3.2.1.7.5A detailed description of all non-volatile fault log dataIncluding:
3.2.1.7.5.1Memory locations of stored data
3.2.1.7.5.2Hardware/software interfaces and methods of data retrieval
3.2.1.7.5.3Parameters stored (pass/fail criteria, tolerances) and correspondence to specific test numbers
3.2.1.7.5.4Other available information (e.g. calibration data) relevant to O-level/depot diagnostics
3.2.1.7.5.5When applicable, a complete listing (with pass/fail criteria) of all BIT test and calibration measurement data available for supplemental diagnostic- Diagnostic Test Module (DTM) useAlong with procedure for data retrieval.
3.2.1.8Descriptions of each applicable BIT mode(e.g., Power-up BIT (PUBIT) or Start-up BIT (SBIT)), Background/Periodic BIT (BBIT or PBIT), Initiated BIT (IBIT), Maintenance BIT (MBIT)), including a flowchart of BIT test sequences and timelines. Include detailed test descriptions to define the test objective, test mechanization, and method for setting the test threshold for each Built-In Test (BIT). Identify the relationship of test tolerances to hardware requirements being tested, along with pass/fail criteria for each BIT. Additionally, identify the relationship between the BIT test levels/tolerances and the corresponding Weapon Replaceable Assembly (WRA) / Line Replaceable Unit (LRU) and Shop Replaceable Assembly (SRA) / Shop Replaceable Unit (SRU) depot test levels/tolerances. DATA DELIVERY: INTERMEDIATE and update at FINAL.
3.2.1.9Detailed descriptions of each test executed during at least one BIT modeIncluding definition of the test objective, test mechanization and method for setting the test. Identify the relationship of test tolerances to hardware requirements being tested, along with pass/fail criteria. DATA DELIVERY: INTERMEDIATE and update at FINAL.
3.2.1.10For non-digital tests relationships between the test levels/tolerances of BIT and the corresponding off-aircraft black box/module testsDATA DELIVERY: INTERMEDIATE and update at FINAL.
3.2.1.11A detailed description of all false alarm filtering(i.e., "M" of "N" event or persistence counting) and mitigation techniques used. DATA DELIVERY: INITIAL, update at INTERMEDIATE and update at FINAL.
3.2.1.12Recommended mechanisms and plan for adjusting BIT accept/reject and false alarm filtering thresholdsFor pre-production and production equipment. DATA DELIVERY: INTERMEDIATE, and update at FINAL.
3.2.1.13Provide a description to address the recording and evaluation of BIT test results by BIT fault detection, fault isolation and mode assessment softwareFlowcharts and/or tables depicting the logic used by BIT to achieve unambiguous fault isolation for the system. DATA DELIVERY: INTERMEDIATE and update at FINAL.
3.2.1.14Technical justification for any noncompliance of BIT performance, along with achievable levelsDATA DELIVERY: INITIAL, update at INTERMEDIATE and update at FINAL.
3.2.1.15For any failures or group of failures identified in Section C, as undetectable or poorly isolated, other than excluded or no effect, provide rationale justifying lack of coverage and recommend alternative detection(e.g., potential aircraft level BIT tests, pilot observations, etc.). Design approaches or trade-offs that were considered to improve fault coverage should be described, along with the rationale for their rejection. Identify advantages (e.g., reduced cost, reduced false alarm susceptibility, etc.) that may be gained from tests using other interfacing avionics. DATA DELIVERY: INTERMEDIATE and update at FINAL.
3.2.1.16A description of diagnostic advantages that may be gained from tests using other interfacing avionicsDATA DELIVERY: INTERMEDIATE and update at FINAL.
3.2.1.17Justification for uses of a WRA (LRU) failure indicator other than that specifiedDATA DELIVERY: INTERMEDIATE and update at FINAL.
3.2.1.18The time required determining a go or no-go condition of the equipment in each of the BIT operating modesDATA DELIVERY: INTERMEDIATE and update at FINAL.
3.3BIT false alarm design mitigation (FADM) analysisThis section of the document provides a qualitative false alarm mitigation analysis for the equipment. The analysis is to be proactively used to guide the hardware and software design, mitigating susceptibility to Built-In Test (BIT) False Alarms and Can Not Duplicates (CNDs). The following "lessons-learned" checklist is to be used to assess each black box and module design, as well as the overall design, documenting the hardware and software features provided by each. The Supplier is encouraged to incorporate additional field or factory lessons learned that may apply to the design. DATA DELIVERY: INTERMEDIATE, and update at FINAL. The False Alarm Mitigation Checklist covers Software Design BIT Concerns and Hardware Design BIT Concerns, with columns for Potential False Alarm Characteristics/Causes, Susceptibility (H, M, L or N/A), and Comments/Mitigation Efforts.
3.4BIT FD/FI and test verticality analysisThis section of the document provides a quantitative, failure rate-weighted BIT fault detection/fault isolation (FD/FI) and test verticality model for the equipment, to be used in both design and assessment of BIT performance capabilities. This analysis addresses black box and module level Fault Detection/Fault Isolation (FD/FI) as described in the Procurement specification. The Built-In Test (BIT) FD/FI and test verticality assessment, along with supporting data, are to include the following elements and conform to the specified worksheet format. Any modifications to the content or format defined herein require written NAVAIR approval. Additional columns may be added to facilitate computations as desired. The general approach is to assess the BIT and off-aircraft coverage for each circuit card/module when installed in the aircraft system, then combine those results into an assessment of each black box or system, as applicable.
3.4.1Ground rules and assumptions
3.4.1.1The following ground rules and assumptions are to be used in preparing the BIT analysis worksheetsGround rules and assumptions can be added or deleted subject to written NAVAIR approval.
3.4.1.1.1Component failure rates are to be taken from the Reliability Prediction
3.4.1.1.2Each component failure mode and its effect on normal system operational performance are evaluated independently of any other component failure modes(a single-point failure philosophy).
3.4.1.1.3The analysis includes only failure modes of electronic/electrical component (circuitry), Radiofrequency (RF) cabling, and electromechanical componentsTherefore, connectors, PCBs, solder connections and wiring are excluded between Shop Replaceable Assemblies (SRAs) / Shop Replaceable Units (SRUs) and external Weapon Replaceable Assemblies (WRAs) / Line Replaceable Units (LRUs) are excluded.
3.4.1.1.4Failure modes of components used for the following purposes, that do not affect normal system operational performance, are excludedNormal system operational performance means that all functional circuits, safety circuits, and BIT circuits are fully capable of performing their intended functions.
3.4.1.1.4.1Failure modes of components employing "good engineering practices"(e.g. redundant pull-up resistors, decoupling or filtering capacitors, etc.) which do not affect normal system operational performance are excluded.
3.4.1.1.4.2Failure modes of components dedicated to test interface circuitry(e.g., software debug, signature/ configuration. resistors, test point isolation resistors, other circuits for depot test use only, etc.) which do not affect normal system operational performance are excluded.
3.4.1.1.4.3Failure modes of components provided specifically for safety circuitry required to protect the depot maintainer, that do not impact normal system operational performance are to be classified as "no effect" for two-level OEM Depot programs
3.4.1.1.4.4All spare/growth circuitry that does not impact normal system operational performance, is to be classified as "no effect"
3.4.1.1.5Failure modes of circuitry that cause a power shutdown or a failure to communicate with the external system will render the WRA (LRU) inoperable ("Dead Box")Credit may be taken for BIT fault detection and isolation, if the external system (i.e. Mission Computer) does the following:
3.4.1.1.5.1Detects the WRA (LRU) or system failure(dependent on having a "Ready" signal provided to Mission Computers (MC)).
3.4.1.1.5.2Reports the corresponding loss of functionality to the pilot
3.4.1.1.5.3Reports the faulty black box to the ground crew(substantiation of how the fault is isolated is required).
3.4.1.1.6A test is defined as a specific BIT or off-aircraft measurement/observation that verifies one or more attributes of the system
3.4.1.1.7Failures of Built-In Test (BIT) circuitry that only affect BIT operation are to be included in the analyzed failure rate unless specifically excluded by the Performance/Procurement Specification
3.4.1.1.8Overload and protection circuitry that does not contribute to the normal operational system is excluded(unless failure of circuitry would cause a functional failure).
3.5Definitions
3.5.1Fault detectionCalculate fault detection for detection by Power-up/Start-up Built-In Test (PUBIT), Background/Periodic Built-In Test (PBIT), and the combined BIT modes (PBIT + Initiated Built-In Test (IBIT)) for both the Weapon Replaceable Assembly (WRA) / Line Replaceable Unit (LRU) and Shop Replaceable Assembly (SRA) / Shop Replaceable Unit (SRU) if required. The total analyzed failure rate detected by PUBIT, PBIT and the combined BIT modes (PBIT + IBIT) is listed on the WRA (LRU) worksheet. Fault detection is defined as: % Fault Detection = (Total Detected Failure Rate / Total Analyzed Failure Rate) x 100 Notes: Total Analyzed Failure Rate = Total Failure Rate - Excluded Failure Rate. The Total Analyzed Failure Rate can be obtained from the spreadsheet directly. Total Detected Failure Rate can be obtained from the bottom of each column under detected failure rate for PUBIT, PBIT and the combined BIT modes. NOTE: Total Detected Failure Rate = Total Analyzed Failure Rate - Undetected Failure Rate
3.5.2IsolationCalculate fault isolation for unambiguous isolation to one (1) Weapon Replaceable Assembly (WRA) / Line Replaceable Unit (LRU). The WRA (LRU) summary worksheets summarize this data. Fault Isolation is defined as: % Fault Isolation = (Total Isolated Failure Rate / Total Detected Failure Rate) x 100 Notes: Total Detected Failure Rate via all BIT modes (PBIT + IBIT) can be obtained from the WRA (LRU) -level spreadsheet directly. Total Detected (PBIT + IBIT) Failure Rate isolated to one (1) WRA (LRU) by BIT can be obtained from the WRA (LRU) -level spreadsheet directly.
3.5.3O-level fault detectionCalculate fault detection for Organizational-level (O-level) detection by any method for the Weapon Replaceable Assembly (WRA) / Line Replaceable Unit (LRU). The total analyzed failure rate (Verticality) and Overall BIT/O-Level Detection data is listed on the WRA (LRU) worksheet. Fault detection is defined as: % Fault Detection (Verticality) = (Total Overall BIT/O-Level Detected Failure Rate / Total Analyzed Failure Rate) x 100 Notes: Total Analyzed Failure (verticality) can be obtained from the spreadsheet directly. Total Detected Failure Rate (verticality) can be obtained from the spreadsheet directly.
3.5.4Depot WRA (LRU) verticalityCalculate Depot Weapon Replaceable Assembly (WRA) / Line Replaceable Unit (LRU) verticality for the WRA / LRU. The total analyzed failure rate (Verticality) and Depot detection data is listed on the WRA (LRU) worksheet. Verticality is defined as: % Depot Verticality (Verticality) = (Total Depot Verticality Failure Rate / Total Analyzed Failure Rate) x 100 Notes: Total Analyzed Failure Rate (verticality) can be obtained from the spreadsheet directly. Total Depot Verticality Failure Rate can be obtained from the spreadsheet directly.
3.5.5ATP WRA (LRU) verticalityDepot ATP verticality must be calculated for the WRA (LRU). The total analyzed failure rate (Verticality) and ATP detection data is listed on the WRA (LRU) worksheet. Verticality is defined as: % Depot Verticality (Verticality) = (Total ATP Verticality Failure Rate / Total Analyzed Failure Rate) x 100 Notes: Total Analyzed Failure Rate (verticality) can be obtained from the spreadsheet directly. Total ATP Verticality Failure Rate can be obtained from the spreadsheet directly.
3.6Circuit failure classificationAll components are to be classified per Table 1. Classes 4 and 5 are excluded from the analysis calculations (but not from the worksheets) because they do not impact the mission.
3.7Failure mode allocation/distribution of componentsThe allocation/distribution of component failure modes to be used in the BIT analysis is shown in Table 2. Any deviation and/or addition from this table requires NAVAIR concurrence.
3.8SRA (SRU) BIT analysis worksheet formatThe BIT Analysis worksheet for each circuit card/module contained in the system includes columns of data describing, for each component: the reference designator, part identification, component failure rate, failure mode, failure rate per mode, failure classification and applicability, circuit function, effects of failure at the SRA/SRU, WRA/LRU, and pilot/system level, the applicable Power-up/Start-up, Background/Periodic, Initiated, and Maintenance BIT test identifiers, the corresponding detected failure rates by each BIT mode and combined BIT modes, the fault isolation results (to 1, 2, or 3 WRAs (LRUs) or SRAs (SRUs)) by each BIT mode, the analyzed failure rate (BIT and Verticality), BIT indication codes, BIT and WRA (LRU) depot test information, and the shop level and ATP test identifiers. The top of the first page of each worksheet includes the following summary information: WRA (LRU) name; SRA (SRU) name; SRA (SRU) Module part number; SRA (SRU) Module schematic drawing number and revision used to perform the analysis; SRA (SRU) Module reference designator; total failure rate of the SRA (SRU) module; total analyzed SRA (SRU) module failure rate (total less excluded); and failure class legend (refer to Table 1). At the bottom of columns 5, 15-20, and 28-30 indicate the total for each column. This total indicates the ability of BIT to detect failures within the Weapon Replaceable Assembly (WRA) / Line Replaceable Unit (LRU) and isolate to the correct WRA (LRU). At the bottom of columns 8, 10, 30a, and 32 indicate the total for each column; this total will be used to assess the verticality of the testing methods.
3.9WRA (LRU) BIT analysis worksheet formatEach WRA (LRU) BIT/Verticality worksheet is a summary of the SRA (SRU) BIT Analysis Worksheets. The Weapon Replaceable Assembly (WRA) / Line Replaceable Unit (LRU) BIT/Verticality Analysis worksheet includes columns of data, for each Shop Replaceable Assembly (SRA) / Shop Replaceable Unit (SRU), describing: the SRA (SRU) reference designator, name, and part number; total and total analyzed (BIT) SRA (SRU) failure rate; detected failure rate by PUBIT, PBIT, IBIT, and MBIT; total BIT detection; isolation to 1 WRA (LRU) via combined BIT modes and via PUBIT, MBIT, IBIT, and PBIT individually; detected BIT failure rate isolated to 1, 2, or 3 SRAs (SRUs); detected PBIT + IBIT failure rate isolated to 1, 2, or 3 SRAs (SRUs); comments; total analyzed (Verticality) SRA (SRU) failure rate; total overall BIT/O-level fault detection; shop-level fault detection; and ATP verticality. At the top of the first page of each WRA / LRU worksheet, include the following summary information: WRA (LRU) name; WRA (LRU) Assembly number (part number); WRA (LRU) Reference Designator. At the bottom of columns 4 through 18 indicate the total for each column. These totals indicate the ability of Built-In Test (BIT) to detect failures within the Weapon Replaceable Assembly (WRA) / Line Replaceable Unit (LRU) and isolate to the correct WRA / LRU. At the bottom of columns 13 through 16, indicate the total for each column. These totals are used to indicate the overall verticality of the testing methods.
3.10System BIT/verticality analysis summary sheet formatThe System Level BIT/Verticality Analysis Summary Sheet is a summary of the performance of Weapon Replaceable Assemblies (WRAs) / Line Replaceable Units (LRUs). The System BIT/Verticality Analysis Summary Sheet contains columns of data for: % analyzed failure rate detected by PUBIT, MUBIT, PBIT, IBIT, and PBIT + IBIT; % analyzed failure rate detected by the combined BIT modes; % detected failure rate isolated to 1 WRA (LRU) by BIT; % detected failure rate isolated to 1, </=2, or </=3 SRA (SRU) by PBIT + IBIT; % detected failure rate at the O-Level (Verticality); % detected failure rate at the depot level (Verticality); and % detected failure rate using the ATP. For systems with multiple WRAs / LRUs, provide a system level BIT/Verticality analysis summary sheet in a similar manner.
3.11Failure Mode and Effects Analysis FMEAFor programs where a separate Failure Mode and Effects Analysis (FMEA) or Failure Mode, Effects, and Criticality Analysis (FMECA) System Design Language (SDL) item is not ordered, this section fulfills the intent of the Failure Mode and Effects Analysis (E-14.04/E-49), required for support of System Safety Engineering (System Safety Hazard Analysis) and Product Support Engineering (Avionics Maintenance Information Data System (AMIDS) or Configuration and Fault Reporting System (CF/CRS) and Tech Pubs development). This analysis extends the Built-In Test/Test Verticality (BIT/TV) Analysis and provides for the identification and classification of failure modes and safety hazards per the detailed ground rules provided herein. For each component failure mode of the avionics system analyzed in section A, the FMEA analysis includes the following information. In addition to the component failure modes identified in the BIT Analysis, the FMEA also addresses external failure modes and failure effects of damaged Weapon Replaceable Assembly (WRA) connectors, aircraft wiring, and associated airborne equipment. For this analysis, fault detection and isolation coverage by all available means to the operator/maintainer (including BIT) is identified. Provided that the BIT/TV analysis is used as its baseline, this section may be tailored to a functional analysis, subject to Customer written approval.
3.11.1WRA/LRU Reference Designator(per BIT Analysis).
3.11.2SRA/SRU Reference Designator(per BIT Analysis).
3.11.3Component Reference Designator(per BIT Analysis).
3.11.4Circuit Function(per BIT Analysis).
3.11.5Failure Mode(per BIT Analysis).
3.11.6Mission Phase/Operational Mode(per MIL-STD-1629A, Task 101).
3.11.7SRA/SRU (local) Failure Effect(per MIL-STD-1629A, Task 101).
3.11.8WRA/LRU (next level) Failure Effect(per MIL-STD-1629A, Task 101).
3.11.9Aircraft (end) Failure Effect(per MIL-STD-1629A, Task 101).
3.11.10Failure Detection/Isolation Method(see BIT Analysis & MIL-STD-1629A, Tasks 101 & 103).
3.11.11Compensating Provisions(per MIL-STD-1629A, Task 101).
3.11.12Severity Classification(per MIL-STD-1629A, Task 101).
3.11.13Remarks(per MIL-STD-1629A, Task 101).
3.11.14Failure Probability/Failure Rate Data Source(per MIL-STD-1629A, Task 102).
3.11.15Failure Effect Probability(per MIL-STD-1629A, Task 102).
3.11.16Failure Mode Ration(per MIL-STD-1629A, Task 102).
3.11.17Operating Time(per MIL-STD-1629A, Task 102).
3.11.18Engineering Failure Mode MTBF(per MIL-STD-1629A, Task 103).

References

DI-SESS-82078A, Integrated Health Management System (IHMS) Description and Data Architecture (DDA) https://quicksearch.dla.mil

DI-SESS-81497B, Reliability and Maintainability Predictions Report https://quicksearch.dla.mil

DI-SESS-81603, Maintainability and Built in Test Demonstration Report https://quicksearch.dla.mil

DI-SESS-81604B, Maintainability and Built in Test Demonstration Procedure https://quicksearch.dla.mil

Figures

Figure 1: TABLE 1 - Circuit Failure Classification

Figure 1. TABLE 1 - Circuit Failure Classification

Figure 1: TABLE 1 - Circuit Failure Classification (Continued)

Figure 1. TABLE 1 - Circuit Failure Classification (Continued)

Figure 2: TABLE 2 - Failure Mode Allocation/Distribution of Components

Figure 2. TABLE 2 - Failure Mode Allocation/Distribution of Components

Figure 2: TABLE 2 - Failure Mode Allocation/Distribution of Components (Continued)

Figure 2. TABLE 2 - Failure Mode Allocation/Distribution of Components (Continued)

Figure 2: TABLE 2 - Failure Mode Allocation/Distribution of Components (Continued)

Figure 2. TABLE 2 - Failure Mode Allocation/Distribution of Components (Continued)

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